Verification engineer for an out-of-order processor and accelerators (RE1/RE2)

Application deadline:

The eProcessor EuroHPC project combines open source software (SW)/hardware (HW) to deliver the first completely open source European full stack ecosystem based on a new RISC-V CPU, coupled to multiple diverse accelerators that target traditional HPC and extend into mixed precision workloads for High Performance Data Analytics (HPDA), (AI, ML, DL and Bioinformatics). eProcessor will be extendable (open source), energy-efficient (low power), extreme-scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on-chip and/or off-chip components).

eProcessor combines cutting edge research utilizing SW/HW co-design to achieve sustained processor and system performance for (sparse and mixed-precision) HPC and HPDA workloads by combining a high performance low power (architecture and circuit techniques) out-of-order processor core with novel, adaptive on-chip memory structures and management, as well as fault tolerance features. These software-hardware co-design solutions span the full stack from applications to runtimes, tools, OS, and the CPU and accelerators. This can only be done with a combination of SW simulation, HW emulation using FPGAs, and real ASIC prototypes that demonstrate the full stack feasibility of the hardware and software, in a modern technology node that can easily be adopted for a near-future HPC implementation.

We are seeking one talented and motivated professional with expertise in modern Design Verification methodologies, targeting ASICs tapeouts.